Increased power dissipation is becoming a major challenge in the design of integrated circuits, because it causes numerous problems including reduced battery life in mobile systems, expensive packaging and cooling solutions, and potential chip failures. Among the various factors contributing to power dissipation, leakage (or static power) dissipation becomes increasingly important with technology scaling and is predicted to surpass dynamic power dissipation at around the 65 nm technology node.
Efforts have been made to investigate various methods for reducing and controlling leakage dissipation in circuits. Powergating is a highly effective technique which uses integrated switches, e.g., NFET and PFET, to cut off the leakage paths between the power supply terminals in an idle state to reduce significant leakage. Researches have been done at the level of circuit implementation required to achieve efficient powergating solutions.
For example, FIG. 1 shows a schematic view of a powergating implementation 10 of a powergated logic 12. In FIG. 1, the powergating is implemented by placing an NFET 14 (also called a footer) between the ground terminal of logic 12 and chip ground 16. The net connecting the ground terminals of powergated logic 12 and the drain of the NFET 14 is named as a virtual ground (vgnd) 18. When NFET 14 is turned off by its control signal “sleep_n”, leakage through logic 12 is reduced. A similar effect can be achieved by using a PFET 20 (or a header) between chip Vdd supply 22 and the Vdd terminal of logic 12. A drain terminal of header 22 is named a virtual power 14.
FIG. 2 shows a schematic view of a powergated macro 50. Macro 50 includes a combinational logic block 52 and latches 54 and 56. The outputs of combinational logic 52 may be fed into latches 54 and 56 to produce outputs of macro 50 (68 and 72), or may become outputs of macro 50 directly (66 and 70). Outputs of the macro may be fed into fence circuits 60, 62 and 64 that are attached to powergated macro 50. Typically, latch outputs (68 or 72) may also be fed back to the input of combinational logic 52. Here, the feedback loop is eliminated here for simplicity. In a powergated macro (50), typically there will be multiple small footer elements all tied in parallel between a virtual ground and a chip ground while ground terminals of all logic gates and latches will be tied to the virtual ground. These footers are shown as a single footer 58 in FIG. 2. Footer 58 is controlled by a sleep signal “sleep_n” similar to the configuration shown in FIG. 1. The output of footer 58 controls the ground terminals of combinational logic block 52 and latches 54 and 56 in macro 50. When powergating is activated by control signal “sleep_n”, footer 58 is turned off, which causes the outputs of combinational logic 52 to float, and causes latches 54 and 56 to lose state. As a consequence, in the powergated state, macro outputs (66, 68, 70 and 72) will tend to float, i.e. the voltage at the output will neither be close to power supply Vdd (not shown), nor will it be close to 0 volts, rather it may be in-between and close to Vdd/2. If such floating macro outputs are inputs into gates in a non-powergated macro, then the gates of the non-powergated macro may leak heavily. It is also possible that a non-powergated element will malfunction if the input is floating or in an indeterminate state. To prevent such problems during powergating, outputs 68, 70 and 72 of powergated macro 50 are fed into fence circuits 60, 62 and 64. In FIG. 2. Fence 60 forces a “0” state (febce0) at the outputs when the control “fence_en” is activated and fence 62 and 64 force states “1” (fence1) at the outputs. Fence circuits 60, 62 and 64 are controlled by a fence enable “fence_en” signal which is used to turn the fence functions on and off. When a fence (60, 62, or 64) is disabled or turned off, the value at the fence output is the same as the value at the fence input. When a fence is enabled, a fence0 (60) will have a “0” at the output regardless of the input, while a fence1 (62 and 64) will have a “1” at the output. It should be noted that in FIG. 2, there is no fence circuit at output 66, since output 66 goes to another simultaneously powergated macro (not shown), which requires no fence circuit.
Register-transfer level (RTL) modeling of powergated logic, like those shown in FIG. 2, is essential to simulate and verify that a hierarchical element including a powergated logic works properly. When a logic is powergated, the footer, for example, is connected to the ground pin of every logic element. So one approach to modeling powergating at the RTL level is to instantiate a footer, for example, in the RTL model, and to instantiate all the logics as structural elements (gates, latches), and connect the footer to the ground pin of these structural elements. Such a model is referred to as a detailed modeling style, for illustrative purpose. There are several drawbacks of this detailed modeling style as listed below:
(a) the detailed modeling style models the structural as opposed to the behavioral characteristic of a powergated macro, which reduces design productivity and makes it difficult to understand and code;
(b) typically, VHDL (a language usually used for simulating an integrated circuit) libraries of gates do not have power ports corresponding to the Vdd and Gnd pins of the gates in a gate-level or a transistor level implementation (i.e., structural characteristic), so that in a detailed model, all the gates in the VHDL library are require to add extra power pins, which increases complexity of the library and the VHDL description of the macro; and
(c) The simulation time for a detailed model is quite high compared to models that do not include power terminals such as Vdd or Gnd on every logic element.
Based on the above, there is a need to model a powergated macro (or logic) in a behavioral style. There is also a need to model a powergated macro (or logic) in a manner that makes the coding easier using the existing simulation languages such as VHDL.